MC68HC05X4 Rev 1.0
MOTOROLA
Core Timer
103
Core Timer
General Description
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Real time interrupts (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Computer operating properly (COP) watchdog timer . . . . . . . . . . . .105
Core timer registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Core timer control and status register (CTCSR). . . . . . . . . . . . . .106
Core timer counter register (CTCR) . . . . . . . . . . . . . . . . . . . . . . .108
Core timer during WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Core timer during STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Introduction
The MC68HC05X4 has a 15-stage ripple counter called the core timer
(CTIMER). Features of this timer are: timer overflow, power-on reset
(POR), real time interrupt (RTI) with four selectable interrupt rates, and
a computer operating properly (COP) watchdog timer.
As shown in
Figure 1
, the timer is driven by the internal bus clock divided
by four with a fixed prescaler. This signal drives an 8-bit ripple counter.
The value of this 8-bit ripple counter can be read by the CPU at any time,
by accessing the CTIMER counter register (CTCR) at address $09. A
timer overflow function is implemented on the last stage of this counter,
giving a possible interrupt at the rate of f
OP
/1024. The POR signal
(t
PORL
) is also derived from this register, at f
OP
/32. The counter register
circuit is followed by four more stages, with the resulting clock
(f
OP
/16384) driving the real time interrupt circuit. The RTI circuit consists
of three divider stages with a 1-of-4 selector. The output of the RTI circuit
is further divided by eight to drive the COP watchdog timer circuit. The
RTI rate selector bits, and the RTI and CTIMER overflow enable bits and
1-ctimer
F
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n
.