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參數(shù)資料
| 型號(hào)： | MC68HC05V12CFNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 69/135頁(yè) |
| 文件大?。?/td> | 2080K |
| 代理商： | MC68HC05V12CFNR2 |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
General Description
Technical Data
MC68HC05V12 — Rev. 2.0
32
General Description
MOTOROLA
16-bit timer. See Section 9. 16-Bit Timer for more details on the
operation of the timer subsystem.
PB4 and PB5 are shared with the pulse width modulator output pins
(PWMA and PWMB). See Section 11. Pulse Width Modulators
(PWMs) for more details on the operation of the PWMs.
1.6.10 PC0–PC7
These eight I/O lines comprise port C. The state of any pin is software
programmable and all port C lines are configured as inputs during
power-on or reset. All eight pins are connected via an internal gate to the
IRQ interrupt function. When the IRQ interrupt function is enabled, all the
port C pins will act as negative edge-sensitive IRQ sources. See
Section 7. Parallel Input/Output (I/O) for more details on the I/O ports.
1.6.11 PD0–PD4/AD0–AD4
When the A/D converter is disabled, PD0–PD4 are general-purpose
input pins. The A/D converter is disabled upon exiting from reset. When
the A/D converter is enabled, one of these pins is the analog input to the
A/D converter. The A/D control register contains control bits to direct
which of the analog inputs are to be converted at any one time. A digital
read of this pin when the A/D converter is enabled results in a read of
logical zero from the selected analog pin. A digital read of the remaining
pins gives their correct (digital) values. See Section 13. Analog-to-
Digital (A/D) Converter for more details on the operation of the A/D
subsystem.
1.6.12 TXP and RXP
These pins provide the I/O interface for the BDLC subsystem. See
details on the operation of the BDLC.
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