參數(shù)資料
型號(hào)： MC68HC05SR3CP
廠(chǎng)商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 39/96頁(yè)
文件大?。?/td> 612K
代理商： MC68HC05SR3CP
MOTOROLA
5-8
MC68HC05SR3
RESETS AND INTERRUPTS
5
TIF — Timer Interrupt Flag
1 (set)
–
A timer interrupt (timer overow) has occurred.
0 (clear) –
A timer interrupt (timer overow) has not occurred.
The I-bit in the CCR must be cleared in order for the timer interrupt to be processed. The interrupt
will vector to the interrupt service routine at the address specied by the contents in $1FF6-$0FF7.
5.2.2.4
Keyboard Interrupt (KBI)
Keyboard interrupt function is associated with Port A pins. The keyboard interrupt function is
enabled by setting the keyboard interrupt enable bit KBIE (bit 7 of MCR at $0C) and the individual
enable bits KBE0-KBE7 (bits 0-7 of KBIM at $0B). When the KBEx bit is set, the corresponding
Port A pin will be congured as an input pin, regardless of the DDR setting, and a 20K
pull-up
resistor is connected to the pin, as shown in Figure 5-4. When a high to low transition is sensed
on the pin, a keyboard interrupt will be generated. An interrupt to the CPU will be generated if the
I-bit in the CCR is cleared.
The keyboard interrupt ag should be cleared in the interrupt service routine (by writing a “1” to
KBIC bit in the MCR at $0C) after the key is debounced. Debouncing will avoid spurious false
triggering.
The keyboard interrupt is negative-edge sensitive only, and the interrupt service routine is
specied by the contents in $1FF4-$1FF5.
Figure 5-4 Keyboard Interrupt Circuitry
Pad Logic
&
Keyboard
request
Interrupt
VDD
&
KBEx of KBIM
&
KBIE bit of MCR
($0C bit 7)
DDR0-DDR7
Internal Data bit (0-7), Port A
PAx
1 input for each of PA0-PA7
(8 input NAND)
20K
TPG
42
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