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參數(shù)資料
| 型號： | MC68HC05SR3CFB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 31/96頁 |
| 文件大小： | 3143K |
| 代理商： | MC68HC05SR3CFB |
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MC68HC05SR3
Freescale
5-1
RESETS AND INTERRUPTS
5
RESETS AND INTERRUPTS
This section describes the reset and interrupt functions on the MCU.
5.1
RESETS
The MC68HC05SR3 can be reset in three ways:
by initial power-on reset function, (POR),
by an active low input to the RESET pin, (RESET), and
by a Low Voltage Reset, (LVR).
All of these resets will cause the program to go to the starting address, specified by the contents
of memory locations $1FFE and $1FFF, and cause the interrupt mask (I-bit) of the Condition Code
Register (CCR) to be set.
5.1.1
Power-On Reset (POR)
The power-on reset (POR) occurs on power-up to allow the clock oscillator to stabilize. The POR
is strictly for power-up conditions, and should not be used to detect any drops in power supply
voltage.
There is an oscillator stabilization delay of tPORL internal processor bus clock cycles after the
oscillator becomes active. The RESET pin will be pulled down internally during these cycles. If the
RESET pin is low (by external circuit) at the end of the tPORL period, the processor remains in the
reset condition until RESET goes high.
5.1.2
RESET Pin
The RESET input pin is used to reset the MCU to provide an orderly software start-up procedure.
When using the external reset, the RESET pin must stay low for a minimum of 1.5tCYC. The
RESET pin is connected to a Schmitt Trigger circuit as part of its input to improve noise immunity.
TPG
35
05SR3.Book Page 1 Thursday, August 4, 2005 1:08 PM
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