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參數(shù)資料
| 型號(hào)： | MC68HC05RC18DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 77/124頁(yè) |
| 文件大?。?/td> | 457K |
| 代理商： | MC68HC05RC18DW |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output (I/O)
General Release Specification
MC68HC05RC18 — Rev. 2.0
56
Parallel Input/Output (I/O)
MOTOROLA
6.4 Port B
Port B is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The address of the port B data register is $0001
and the data direction register (DDR) is at address $0005. Reset does
not affect the data register, but clears the data direction register, thereby
returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port bit to output mode. Each of the port B pins has a
mask programmable interrupt generation option, any of which can be
enabled. When an interrupt option is enabled, this pin may also have a
pullup resistor enabled. There is a choice between two pullup strengths,
either of which may be active for the enabled interrupts. The choice of
whether to enable the pullups and which strength to choose will be the
same for all enabled interrupts circuits. The edge or edge and level
sensitivity of the IRQ pin will also pertain to the enabled port B pins. Be
careful when using port B pins that have the interrupt generation
enabled. Before switching from an output to an input, the data should be
preconditioned to a logic 1 to prevent an interrupt from being generated
or the I bit of the condition code register should be set to prevent any
such generated interrupt from taking immediate effect.
Figure 6-1. Port B Pullup Options
PB7
VDD
DDR BIT
NORMAL PORT CIRCUITRY
AS SHOWN IN FIGURE 2-4
IRQ
TO INTERRUPT
LOGIC
MASK OPTION (PB7IE)
FROM ALL OTHER PORT B PINS
IRQEN
VDD
STRONG
WEAK
MASK OPTION (STRONG/WEAK SEL)
MASK OPTION (PULLUP/ENABLE)
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