參數(shù)資料
型號： MC68HC05RC18DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 74/124頁
文件大?。?/td> 457K
代理商： MC68HC05RC18DW
Resets
Internal Resets
MC68HC05RC18 — Rev. 2.0
General Release Specification
MOTOROLA
Resets
53
NON-DISCLOSURE
AGREEMENT
REQUIRED
5.5.2.5 COP Register
The COP register is shared with the LSB of the unimplemented user
interrupt vector at location $3FF0 as shown in Figure 5-3. Reading this
location returns whatever user data has been programmed at this
location. Writing a 0 to the COPR bit in this location clears the COP
watchdog timer.
5.5.3 Illegal Address
An illegal address reset is generated when the CPU attempts to fetch an
instruction from I/O address space ($0000 to $001F).
Address:
$3FF0
Bit 7
654321
Bit 0
Read:
X
Write:
COPR
Reset:
———————
0
= Unimplemented
Figure 5-3. COP Watchdog Timer Location
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