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參數(shù)資料
| 型號： | MC68HC05RC17DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.097 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 86/128頁 |
| 文件大?。?/td> | 4788K |
| 代理商： | MC68HC05RC17DW |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output (I/O)
General Release Specification
MC68HC05RC17 — Rev. 2.0
Parallel Input/Output (I/O)
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The port A data register is at $0000 and the data
direction register (DDR) is at $0004. Reset does not affect the data
register, but clears the data direction register, thereby returning the ports
to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to
output mode.
7.4 Port B
Port B is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The address of the port B data register is $0001
and the data direction register (DDR) is at address $0005. Reset does
not affect the data register, but clears the data direction register, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the
corresponding port bit to output mode. Each of the port B pins has a
mask programmable pullup device that can be enabled. When the pullup
device is enabled, this pin will also become an interrupt pin. The edge or
edge and level sensitivity of the IRQ pin will also pertain to the enabled
port B pins. Care needs to be taken when using port B pins that have the
pullup enabled. Before switching from an output to an input, the data
should be preconditioned to a logic 1 or the I bit should be set in the
condition code register to prevent an interrupt from occurring.
NOTE:
When a port B pin is configured as an output, its corresponding keyscan
interrupt is disabled, regardless of its mask option.
Figure 7-1. Port B Pullup Option
PB7
VDD
DDR BIT
NORMAL PORT CIRCUITRY
AS SHOWN IN FIGURE 7-2
IRQ
TO INTERRUPT
LOGIC
MASK OPTION (PB7PU)
DISABLED
ENABLED
FROM ALL OTHER PORT B PINS
IRQEN
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