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| 型號(hào)： | MC68HC05PL4CSD |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁(yè)數(shù)： | 54/98頁(yè) |
| 文件大?。?/td> | 1019K |
| 代理商： | MC68HC05PL4CSD |
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GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
16-BIT PROGRAMMABLE TIMER
MC68HC05PL4
9-8
REV 2.0
3.
Read the TSR to arm the OCF for clearing.
4.
Enable the output compare registers by writing to the OCRL. This also
clears the OCF ag bit in the TSR.
5.
Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown in Table 9-1.
9.5
TIMER CONTROL REGISTER (TCR)
The timer control register shown in Figure 9-10 performs the following functions:
Enables input capture interrupts.
Enables output compare interrupts.
Enables timer overow interrupts.
Congure the I/O Port Pin PA2 as input pin for TCAP signal
Congure the I/O Port Pin PA3 as output pin for TCMP signal
Control the active edge polarity of the TCAP signal.
Controls the active level of the TCMP output.
Reset clears all the bits in the TCR with the exception of the IEDG bit which is
unaffected.
ICIE - INPUT CAPTURE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the PB1/
TCAP pin or from CPF2 ag bit of the analog subsystem voltage comparator 2.
Reset clears the ICIE bit.
1 =
Input capture interrupts enabled.
0 =
Input capture interrupts disabled.
Table 9-1. Output Compare Initialization Example
9B
...
B7
B6
BF
...
9A
16
13
17
SEI
...
STA
LDA
STX
...
CLI
OCRH
TSR
OCRL
DISABLE INTERRUPTS
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
ENABLE INTERRUPTS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TCR
R
ICIE
OCIE
TOIE
000
IEDG
OLVL
$0012
W
reset:
000000
U
0
Figure 9-10. Timer Control Register (TCR)
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