參數(shù)資料
型號: MC68HC05P9AVP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 77/90頁
文件大小: 285K
代理商: MC68HC05P9AVP
GENERAL RELEASE SPECIFICATION
MC68HC05P9A
ELECTRICAL SPECIFICATIONS
MOTOROLA
Rev. 2.0
13-5
13.5 SIOP Timing
Table 13-4. SIOP Timing (VDD = 5 V)
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted)
Table 13-5. SIOP Timing (VDD = 3.3 V)
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = -40°C to +125°C, unless otherwise noted)
Num.
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fop(m)
fop(s)
0.25
dc
0.25
fop
1
Cycle Time
Master
Slave
tcyc(m)
tcyc(s)
4.0
tcyc
2
Clock (SCK) Low Time
tcyc
932
ns
3
SDO Data Valid Time
tv
200
ns
4
SDO Hold Time
tho
0—
ns
5
SDI Setup Time
ts
100
ns
6
SDI Hold Time
th
100
ns
NOTE: fop = 2.1 MHz maximum
Num.
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fop(m)
fop(s)
0.25
dc
0.25
fop
1
Cycle Time
Master
Slave
tcyc(m)
tcyc(s)
4.0
tcyc
2
Clock (SCK) Low Time
tcyc
1980
ns
3
SDO Data Valid Time
tv
400
ns
4
SDO Hold Time
tho
0—
ns
5
SDI Setup Time
ts
200
ns
6
SDI Hold Time
th
200
ns
NOTE: fop = 1.0 MHz maximum
SDO
BIT 0
BIT 1
BIT 6
SCK
BIT 7
SDI
BIT 0
BIT 1
BIT 6
BIT 7
1
2
3
4
5
6
Figure 13-1. SIOP Timing Diagram
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