參數(shù)資料
型號: MC68HC05P9AP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 11/158頁
文件大?。?/td> 3885K
代理商: MC68HC05P9AP
SIOP
108
SIOP
Figure 61 shows the timing relationships among the serial clock, data
input, and data output. The state of the serial clock between
transmissions is a logic 1. The first falling edge on the PB7/SCK pin
signals the beginning of a transmission, and data appears at the
PB5/SDO pin. Data is captured at the PB6/SDI pin on the rising edge of
the serial clock, and the transmission ends on the eighth rising edge of
the serial clock.
Figure 61. SIOP Data/Clock Timing
PB5/SDO
The PB5/SDO pin is the SIOP data output. Between transfers, the state
of the PB5/SDO pin reflects the value of the last bit shifted out on the
previous transmission, if there was one. To preset the beginning state,
write to the corresponding port data bit before enabling the SIOP. On the
first falling edge on the PB7/SCK pin, the first data bit to be shifted out
appears at the PB5/SDO pin.
PB6/SDI
The PB6/SDI pin is the SIOP data input. Valid SDI data must be present
for an SDI setup time, t
S, before the rising edge of the serial clock and
must remain valid for an SDI hold time, t
H, after the rising edge of the
serial clock. (See Table 22 and Table 23.)
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
SERIAL CLOCK
DATA OUTPUT
SAMPLE INPUT
LSB
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
MSB
(MSB-FIRST OPTION)
(LSB-FIRST OPTION)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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