參數(shù)資料
型號(hào): MC68HC05P4A
廠商: Motorola, Inc.
英文描述: 28-pin MCU (microcontroller unit) based on the MC68HC05P4(28引腳、基于MC68HC05P4升級(jí)的8位微控制器單元)
中文描述: 28引腳單片機(jī)(微控制器)的基礎(chǔ)上MC68HC05P4(28引腳,基于MC68HC05P4升級(jí)的8位微控制器單元)
文件頁(yè)數(shù): 61/102頁(yè)
文件大?。?/td> 930K
代理商: MC68HC05P4A
Timer
Input Capture Register
MC68HC05P4A — Rev. 6.0
AdvanceInformation
MOTOROLA
Timer
61
8.5 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are
read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition. The level transition which triggers the counter transfer is
defined by the corresponding input edge bit (IEDG). Reset does not
affect the contents of the input capture register.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer
is inhibited until the LSB ($15) is also read. This characteristic causes
the time used in the input capture software routine and its interaction
with the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the
free-running counter transfer since they occur on opposite edges of the
internal bus clock.
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參數(shù)描述
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