參數(shù)資料
型號: MC68HC05P4A
廠商: Motorola, Inc.
英文描述: 28-pin MCU (microcontroller unit) based on the MC68HC05P4(28引腳、基于MC68HC05P4升級的8位微控制器單元)
中文描述: 28引腳單片機(jī)(微控制器)的基礎(chǔ)上MC68HC05P4(28引腳,基于MC68HC05P4升級的8位微控制器單元)
文件頁數(shù): 55/102頁
文件大?。?/td> 930K
代理商: MC68HC05P4A
Simple Serial Input/Output Port (SIOP)
SIOP Registers
MC68HC05P4A — Rev. 6.0
AdvanceInformation
MOTOROLA
Simple Serial Input/Output Port (SIOP)
55
bit and configures the SIOP for slave operation. MSTR may be set at
any time regardless of the state of SPE. Clearing MSTR will abort
any transmission in progress.
7.4.2 SIOP Status Register
This register is located at address $000B and contains only two bits.
SPIF — Serial Peripheral Interface Flag Bit
This bit is set upon occurrence of the last rising clock edge and
indicates that a data transfer has taken place. It has no effect on any
further transmissions and can be ignored without problem. SPIF is
cleared by reading the SSR with SPIF set followed by a read or write
of the serial data register. If it is cleared before the last edge of the
next byte, it will be set again. Reset clears this bit.
DCOL — Data Collision Bit
This is a read-only status bit which indicates that an invalid access to
the data register has been made. This can occur any time after the
first falling edge of SCK and before SPIF is set. A read or write of the
data register during this time will result in invalid data being
transmitted or received.
NOTE:
DCOL is cleared by reading the status register with SPIF set followed by
a read or write of the data register. If the last part of the clearing
sequence is done after another transmission has been started, DCOL
will be set again. If the DCOL bit is set and the SPIF is not set, clearing
Address:
$000B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIF
DCOL
0
0
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-4. SIOP Status Register (SSR)
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