參數(shù)資料
型號(hào): MC68HC05P1ADWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 43/124頁
文件大小: 623K
代理商: MC68HC05P1ADWR2
MC68HC05P1A Rev. 3.0
General Release Specification
MOTOROLA
Memory
25
NON-DISCLOSURE
AGREEMENT
REQUIRED
General Release Specification — MC68HC05P1A
Section 2. Memory
2.1 Introduction
2.2 Introduction
The MC68HC05P1A utilizes 13 address lines to access an internal
memory space covering 8 Kbytes. This memory space is divided into
I/O, RAM, and ROM areas.
2.3 Single-Chip Mode Memory Map
When the MC68HC05P1A is in the single-chip mode, the 32 bytes of I/O,
128 bytes of RAM, 2256 bytes of user ROM, 48 bytes of user page zero
ROM, 32 bytes of test ROM, and 16 bytes of user vectors ROM are all
active, as shown in Figure 2-1.
2.4 Input/Output (I/O) and Control Registers
Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers
at locations $0000–$001F. Reading unimplemented bits will return
unknown states, and writing unimplemented bits will be ignored.
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