參數(shù)資料
型號(hào): MC68HC05P18MDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 17/144頁
文件大?。?/td> 1348K
代理商: MC68HC05P18MDW
Instruction Set
Instruction Types
MC68HC(8)05P18 — Rev. 2.0
Advance Information
MOTOROLA
Instruction Set
113
use a combination of direct addressing and relative addressing. The
direct address of the byte to be tested is in the byte following the opcode.
The third byte is the signed offset byte. The CPU finds the conditional
branch destination by adding the third byte to the program counter if the
specified bit tests true. The bit to be tested and its condition (set or clear)
is part of the opcode. The span of branching is from –128 to +127 from
the address of the next location after the branch instruction. The CPU
also transfers the tested bit to the carry/borrow bit of the condition code
register. Table 12-3 lists the jump and branch instructions.
Table 12-3. Jump and Branch Instructions
Instruction
Mnemonic
Branch if carry bit clear
BCC
Branch if carry bit set
BCS
Branch if equal
BEQ
Branch if half-carry bit clear
BHCC
Branch if half-carry bit set
BHCS
Branch if higher
BHI
Branch if higher or same
BHS
Branch if IRQ pin high
BIH
Branch if IRQ pin low
BIL
Branch if lower
BLO
Branch if lower or same
BLS
Branch if interrupt mask clear
BMC
Branch if minus
BMI
Branch if interrupt mask set
BMS
Branch if not equal
BNE
Branch if plus
BPL
Branch always
BRA
Branch if bit clear
BRCLR
Branch never
BRN
Branch if bit set
BRSET
Branch to subroutine
BSR
Unconditional jump
JMP
Jump to subroutine
JSR
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