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參數(shù)資料
| 型號(hào)： | MC68HC05P18ADWE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 107/130頁(yè) |
| 文件大?。?/td> | 1310K |
| 代理商： | MC68HC05P18ADWE |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Input/Output Ports (SIOP)
Technical Data
MC68HC05P18A
Serial Input/Output Ports (SIOP)
application software, these actions could affect the transmitted or
received data.
Figure 9-1. SIOP Block Diagram
9.3 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave
operation. There are no external mode selection inputs available (for
example, slave select pin).
9.3.1 Serial Clock (SCK)
The state of the SCK output normally remains a logic 1 during idle
periods between data transfers. The first falling edge of SCK signals the
beginning of a data transfer. At this time the first bit of received data is
accepted at the SDI pin and the first bit of transmitted data is presented
at the SDO pin (see Figure 9-2). Data is captured at the SDI pin on the
rising edge of SCK, and the first bit of transmitted data is presented at
the SDO pin. The transfer is terminated upon the eighth rising edge of
SCK.
8-BIT
SHIFT
REGISTER
STATUS
REGISTER
BAUD
RATE
CONTROL
REGISTER
GENERATOR
HCO5 INTERNAL BUS
PH2 CLOCK
SCK
SDI
SDO
76 54 32 10
765 43 21 0
76 54 32 10
I/O
$0B
$0C
$0A
CONTROL
LOGIC
SPE
SDI/PB6
SCK/PB7
SDO/PB5
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC68HC05P18AMDW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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