參數資料
型號: MC68HC05P18A
廠商: Motorola, Inc.
英文描述: Low Cost HCMOS Microcontroller(低成本、8位HCMOS微控制器)
中文描述: 低成本HCMOS微控制器(低成本,8位HCMOS微控制器)
文件頁數: 40/130頁
文件大小: 1200K
代理商: MC68HC05P18A
L
G
R
Interrupts
Technical Data
MC68HC05P18A
40
Interrupts
MOTOROLA
4.3 CPU Interrupt Processing
Interrupts cause the processor to save the register contents on the stack
andtosettheinterruptmask(Ibit)topreventadditionalinterrupts.Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
completed.
When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked (I bit in the
condition code register is clear), and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The SWI is executed the
same as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU puts the register contents
on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$3FF0–$3FFF. If more than one interrupt is pending when the interrupt
vector is fetched, the interrupt with the highest vector location, shown in
Table 4-1
, is serviced first.
A return-from-interrupt (RTI) instruction is used to signify when the
interrupt software service routine is completed. The RTI instruction
Table 4-1. Vector Address for Interrupts and Reset
Register
Flag
Name
Interrupts
CPU
Interrupt
Vector Address
N/A
N/A
Reset
RESET
$3FFE–$3FFF
N/A
N/A
Software
SWI
$3FFC–$3FFD
N/A
N/A
External interrupt
IRQ
$3FFA–$3FFB
TSR
ICF
Timer input capture
TIMER
$3FF8–$3FF9
TSR
OCF
Timer output compare
TIMER
$3FF8–$3FF9
TSR
TOF
Timer overflow
TIMER
$3FF8–$3FF9
N/A
N/A
Unimplemented
N/A
$3FF6–$3FF7
N/A
N/A
Unimplemented
N/A
$3FF4–$3FF5
N/A
N/A
Unimplemented
N/A
$3FF2–$3FF3
N/A
N/A
Unimplemented
N/A
$3FF0–$3FF1
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