參數(shù)資料
型號： MC68HC05LJ5P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 40/85頁
文件大?。?/td> 899K
代理商： MC68HC05LJ5P
November 10, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05LJ5
INPUT/OUTPUT PORTS
MOTOROLA
REV 1
7-7
7.4.3 Input Pin
When an I/O pin is programmed as an input pin, the state of the pin can be deter-
mined by reading the corresponding data register bit. Any writes to the corre-
sponding data register bit for an input pin will be ignored in the sense that the
written value will not be reected on the pin, rather it is only reected in the port
data register. Please refer to Table 7-1 and Table 7-2 for details.
If the corresponding bit in the pull-down/up register is clear (and the pull-down/up
mask option is chosen) the input pin will also have an activated pull-down/up
device. Since the pull-down/up register bits are write-only, bit manipulation should
not be used on these register bits.
7.4.4 I/O Pin Transitions
A "glitch" can be generated on an I/O pin when changing it from an input to an out-
put unless the data register is rst preconditioned to the desired state before
changing the corresponding DDR bit from a zero to a one.
If pull-downs are enabled by mask option, a oating input can be avoided by clear-
ing the pull-down/up register bit before changing the corresponding DDR from a
one to a zero. This will insure that the pull-down device will be activated before the
I/O pin changes from a driven output to a pulled low/high input.
7.4.5 I/O Pin Truth Tables
Every pin on Port A and Port B may be programmed as an input or an output
under software control as shown in Table 7-1 and Table 7-2. All port I/O pins may
also have software programmable pull-down/up devices if selected by the appro-
priate mask option.
Table 7-1. Port A I/O Pin Functions
Table 7-2. Port B I/O Pin Functions
Accesses to
PDURA
at $0010
Accesses to
Data Register
@ $0000
0
1
IN, Hi-Z
OUT
PDURA0-7
DDRA0-7
I/O Pin
PA0-7
*
PA0-7
U
I/O Pin Mode
DDRA
Read/Write
Accesses
to DDRA
@ $0004
Read
Write
Read
Write
* Does not affect input,
but stored to data register
U is undefined
Accesses to
PDURB
at $0011
Accesses to
Data Register
@ $0001
0
1
IN, Hi-Z
OUT
PDURB0-2
DDRB0-2
I/O Pin
PB0-2
*
PB0-2
U
I/O Pin Mode
DDRA
Read/Write
Accesses
to DDRB
@ $0005
Read
Write
Read
Write
* Does not affect input,
but stored to data register
U is undefined
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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