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參數(shù)資料
| 型號(hào)： | MC68HC05L1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 77/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC05L1B |
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MOTOROLA
9-2
MC68HC05L1
LOW POWER MODES
9
9.1.2
ADC during Stop Mode
When Stop mode is entered with the ADC turned on, the ADC clocks are stopped and the ADC is
disabled for the duration of Stop mode, including the 4064 cycle start-up time. If the ADC RC
oscillator is used, it will also be disabled.
When leaving Stop mode, after the 4064-cycle start-up time, the ADC and ADC RC oscillator
resume regular operation. However, a time tADON is required for the ADC circuitry to stabilize.
During tADON, ADC conversion results may be inaccurate.
9.2
Wait Mode
When the MCU enters the Wait mode, the CPU clock is halted. All CPU activities are halted, but
the 16-bit free-running counter and the ADC remain active. Any interrupts from the peripherals will
cause the processor to exit the Wait mode. A reset will also take the MCU out of Wait mode.
The Wait mode power consumption depends on how many systems are active. If a non-reset exit
from the Wait mode is performed (e.g. timer overow interrupt exit), the state of the remaining
systems will be unchanged. If a reset exit from the Wait mode is performed, all the systems revert
to the default reset state.
TPG
74
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