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參數(shù)資料
| 型號： | MC68HC05L1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 51/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC05L1B |
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MOTOROLA
6-2
MC68HC05L1
ANALOG TO DIGITAL CONVERTER
6
6.1
A/D Converter Operation
As shown in Figure 6-1, the A/D converter consists of an analog multiplexer, an 8-bit digital to
analog capacitor array, a comparator and a successive approximation register (SAR).
There are nine options that can be selected by the multiplexer; the AN0 to AN5 input pins, VRH,
(VRH+VRL)/s or VRL. Selection is done via the CHx bits in the ADC Status/Control register. AN0
to AN5 are input points for A/D conversion operations; the others are reference points which can
be used for test purposes. The converter uses VRH and VRL as reference voltages. An input
voltage equal to or greater than VRH converts to $FF. An input voltage equal to or less than VRL,
but greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded.
Each analog input source should use VRH as the supply voltage and should be referenced to VRL
for the ratiometric conversions. To maintain full accuracy of the A/D, three requirements should be
followed:
1) VRH should be equal to or less than VCC;
2) VRL should be equal to or greater than VSS but less than maximum
specications; and
3) VRH–VRL should be equal to or greater than 4 Volts.
The A/D reference inputs (VRH and VRL) are applied to a precision internal digital to analog
converter. Control logic drives this D/A converter and the analog output is successively compared
with the selected analog input sampled at the beginning of the conversion. The conversion is
monotonic with no missing codes.
The result of each successive comparison is stored in the successive approximation register
(SAR) and, when the conversion is complete, the contents of the SAR are transferred to the
read-only Result Data register ($08), and the conversion complete ag, COCO, is set in the
ADC Status/Control register ($09).
Warning: Any write to the ADC Status/Control register will abort the current conversion, reset the
conversion complete ag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared, thus the A/D is disabled.
TPG
50
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