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參數(shù)資料
| 型號(hào)： | MC68HC05L16FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 25/202頁(yè) |
| 文件大?。?/td> | 2285K |
| 代理商： | MC68HC05L16FU |
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Timer System
Technical Data
MC68HC(7)05L16 — Rev. 4.0
120
Timer System
MOTOROLA
Because the timer has a 16-bit architecture, each specific functional
segment (capability) is represented by two registers. These registers
contain the high byte and low byte of that functional segment. Generally,
accessing the low byte of a specific timer function allows full control of
that function; however, an access of the high byte inhibits that specific
timer function until the low byte is accessed also.
NOTE:
The I bit in the condition code register (CCR) should be set while
manipulating both the high byte and low byte register of a specific timer
function to ensure that an interrupt does not occur.
9.3.1 Counter
The key element in the programmable timer is a 16-bit, free-running
counter or counter register preceded by a prescaler that divides the
internal processor clock by four. The prescaler gives the timer a
resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock.
Software can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two
locations: $18–$19 (counter register) or $1A–$1B (counter alternate
register). A read from only the least significant byte (LSB) of the free-
running counter ($19, $1B) receives the count value at the time of the
read. If a read of the free-running counter or counter alternate register
first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19,
$1B) is transferred to a buffer. This buffer value remains fixed after the
first MSB read, even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or counter alternate
register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter
alternate register, if the MSB is read, the LSB must also be read to
complete the sequence.
The counter alternate register differs from the counter register in one
respect: A read of the counter register MSB can clear the timer overflow
flag (TOF). Therefore, the counter alternate register can be read at any
time without the possibility of missing timer overflow interrupts due to
clearing of the TOF.
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