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參數(shù)資料
| 型號： | MC68HC05K3CDWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 97/132頁 |
| 文件大?。?/td> | 1188K |
| 代理商： | MC68HC05K3CDWR2 |
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Parallel Input/Output (I/O)
I/O Port Programming
MC68HC05K3 — Revision 4.0
Technical Data
MOTOROLA
Parallel Input/Output (I/O)
67
7.5.2 Output Pin
When an I/O pin is programmed as an output pin, the state of the
corresponding data register bit determines the state of the pin. The state
of the data register bits can be altered by writing to address $0000 for
port A and address $0001 for port B. Reads of the corresponding data
register bit at address $0000 or $0001 return the state of the data
register bit, not the state of the I/O pin itself. Therefore, bit manipulation
is possible on all pins programmed as outputs.
All pins programmed as outputs have their pulldown devices disabled
regardless of the selected mask option for software programmable
pulldowns or the state of their PDR bits.
7.5.3 Input Pin
When an I/O pin is programmed as an input pin, the state of the pin can
be determined by reading the corresponding data register bit. Any writes
to the corresponding data register bit for an input pin is saved by the
register bit, but not applied to the corresponding I/O pin until the pin is
later programmed to be an output.
If the corresponding bit in the pulldown register is clear (and the mask
option for software programmable pulldowns is selected), the input pin
also has an activated pulldown device.
Read-modify-write instructions, such as bit manipulation, should not be
used on the pulldown registers, since they are write-only.
7.5.4 I/O Pin Transitions
A “glitch” can be generated on an I/O pin when changing it from an input
to an output unless the data register is first pre-conditioned to the
desired state before changing the corresponding DDR bit from a 0 to a 1.
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