參數(shù)資料
型號(hào): MC68HC05K3CDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 107/132頁
文件大小: 1188K
代理商: MC68HC05K3CDWR2
Technical Data
MC68HC05K3 — Revision 4.0
76
8-Bit Timer
MOTOROLA
8-Bit Timer
8.4 COP Watchdog Timer
The computer operating properly (COP) watchdog timer function is
implemented on this device by using the output of the RTI circuit and
further dividing it by eight. The minimum COP reset times are listed in
If the COP circuit times out, an internal reset is generated and the reset
vector is fetched. Preventing a COP timeout is done by writing a logical 0
to the COPC bit at address $03F0 as shown in Figure 8-4. The COPR
register is shared with a user EEPROM byte. This address location is not
affected by any reset signals. Reading this location returns the user
EEPROM byte. When the COPC is cleared, only the final four bits used
to count eight RTI cycles are cleared. The COP watchdog timer can be
enabled/disabled by a mask option.
Address:
$03F0
Bit 7
654321
Bit 0
Read:
Reading $03F0 returns the contents of user EEPROM
Write:
COPC
Reset:
———————
0
= Unimplemented
Figure 8-4. COPR Watchdog Timer Location
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