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| 型號(hào)： | MC68HC05E5DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 114/140頁(yè) |
| 文件大小： | 847K |
| 代理商： | MC68HC05E5DW |
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Motorola Bus (M Bus) Interface
M-Bus Protocol
MC68HC05E5 — Rev. 1.0
General Release Specification
MOTOROLA
Motorola Bus (M Bus) Interface
75
NON-DISCLOSURE
AGREEMENT
REQUIRED
11.5.7 Clock Synchronization
Since wired-AND logic is performed on the SCL line, a high-to-low
transition will affect the devices connected to the bus. The devices start
counting their low period and once a device's clock has gone low, it will
hold the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of
the SCL line if another device clock is still within its low period.
Therefore, the synchronized clock SCL will be held low by the device
with the longest low period. Devices with shorter low periods enter a high
wait state during this time. (See Figure 11-2.) When all devices
concerned have counted off their low period, the synchronized SCL line
will be released and go high. There will then be no difference between
the device clocks and the state of the SCL line and all devices will start
counting their high periods. The first device to complete its high period
will again pull the SCL line low.
11.5.8 Handshaking
The clock synchronization mechanism can be used as a handshake in
data transfer. Slave devices may hold the SCL low after completion of
one byte. In such cases, the device will halt the bus clock and force the
master clock into a wait state until the slave releases the SCL line.
Figure 11-2. Clock Synchronization
SCL
SCL2
SCL1
INTERNAL COUNTER RESET
WAIT
START COUNTING HIGH PERIOD
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05E5P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
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