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參數(shù)資料
| 型號(hào)： | MC68HC05E1CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 8/86頁 |
| 文件大?。?/td> | 709K |
| 代理商： | MC68HC05E1CDW |
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General Release Specication
MC68HC05E1 — Revision 2.0
16
General Description
MOTOROLA
General Description
1.4 Mask Options
There are four mask options on the MC68HC05E1: STOP instruction
(enable/disable), IRQ (Edge-sensitive only or Edge- and level-sensitive),
COP Watchdog Timer (enable/disable), and CPI Rate (1 second, 0.5
second, or 0.25 second).
NOTE:
A line over a signal name indicates an active low signal. For example,
RESET is active low.
1.5 Functional Pin Description
1.5.1 V
DD
and V
SS
Power is supplied to the microcontroller using these two pins. VDD is the
positive supply and VSS is ground.
1.5.2 IRQ (Maskable Interrupt Request)
This pin has a programmable option that provides two different choices
of interrupt triggering sensitivity. The options are:
1. negative edge-sensitive triggering only, or
2. both negative edge-sensitive and level-sensitive triggering.
The MCU completes the current instruction before it responds to the
interrupt request. When IRQ goes low for at least one tILIH, a logic one
is latched internally to signify an interrupt has been requested. When the
MCU completes its current instruction, the interrupt latch is tested. If the
interrupt latch contains a logic one, and the interrupt mask bit (I bit) in the
condition code register is clear, the MCU then begins the interrupt
sequence.
If the option is selected to include level-sensitive triggering, the IRQ input
requires an external resistor to V
DD for “wire-OR” operation.
The IRQ pin contains an internal Schmitt trigger as part of its input to
improve noise immunity. Refer to 3.7 Interrupts for more detail.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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