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參數(shù)資料
| 型號： | MC68HC05E1CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 64/86頁 |
| 文件大?。?/td> | 709K |
| 代理商： | MC68HC05E1CDW |
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Timer, Phase-Locked Loop, and Custom Periodic Interrupt
Phase-Locked Loop Synthesizer
MC68HC05E1 — Revision 2.0
General Release Specication
MOTOROLA
Timer, Phase-Locked Loop, and Custom Periodic Interrupt
67
the specified frequency. The high bandwidth driver is then disabled
and BWC is cleared by internal circuitry. Reset clears this bit.
PLLON — PLL On
This bit activates the synthesizer circuit without connecting it to the
control circuit. This allows the synthesizer to stabilize before it can
drive the CPU clocks. When this bit is cleared, the PLL is shut off.
Reset sets this bit.
NOTE:
PLLON should not be cleared while using the PLL to drive the internal
processor clock, i.e. when BCS is high. If the internal processor clock is
driven by the PLL, clearing the PLLON bit would cause the internal
processor clock to stop. Exercise caution when using these bits.
VCOTST — VCO Test
This bit is used to isolate the loop filter from the VCO in order to
facilitate testing. When clear, the low bandwidth mode of the PLL filter
is disabled. When set, the loop filter operates as indicated by the
values of AUTO and BWC. This bit is always set when AUTO=1 as
security when running in automatic mode. Reset sets this bit.
NOTE:
This bit is intended for use by Motorola to test and characterize the PLL.
The user should always have this bit set to 1.
Table 6-3. Loop Filter Bandwidth Control
AUTO
BWC
VCOTST
HIGH BANDWIDTH
LOW BANDWIDTH
0
OFF
0
1
OFF
ON
0
1
0
ON
OFF
01
1
ON
1
X
1
AUTO
ON
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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