Interrupts
External Interrupt (IRQ or Port B)
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Interrupts
43
N
O
N-D
I
SC
L
O
SU
R
E
AG
R
EEMENT
R
E
Q
U
IR
ED
When any of the port B pullups are enabled, each pin becomes an
additional external interrupt source which is executed identically to the
IRQ pin. Port B interrupts follow the same edge/edge-level selection as
the IRQ pin. The branch instructions BIL and BIH also respond to the
port B interrupts in the same way as the IRQ pin. See 7.4 Port B.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-
only trigger operation is selectable. The sensitivity is software-controlled
by the IRQ bit in the option register ($3FDF).
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse can be latched
and serviced as soon as the I bit is cleared.
Table 4-1. Vector Addresses for Interrupts and Resets
Function
Source
Local Mask
Global Mask
Priority
(1 = Highest)
Vector
Address
Reset
Power-on reset
None
1
$3FFE–$3FFF
RESET pin
COP watchdog
Software interrupt (SWI)
User code
None
Same priority
as instruction
$3FFC–$3FFD
External interrupt
IRQ pin
None
I bit
2
$3FFA–$3FFB
Port B pins
Timer interrupts
ICF bit
ICIE bit
I bit
3
$3FF8–$3FF9
OCF bit
OCIE bit
TOF bit
TOIE bit
SCI interrupts
TDRE bit
TCIE bit
I bit
4
$3FF6–$3FF7
TC bit
RDRF bit
RIE bit
OR bit
IDLE bit
ILIE bit
SPI interrupts
SPIF bit
SPIE bit
I bit
5
$3FF4–$3FF5
MODF bit