參數(shù)資料
型號(hào)： MC68HC05C8FB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 98/156頁
文件大?。?/td> 1755K
代理商： MC68HC05C8FB
Resets
Advance Information
MC68HC05C8A — Rev. 4.0
46
Resets
MOTOROLA
For additional information, refer to Figure 13-8. Power-On Reset
5.4 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a
period of one and one-half machine cycles (tRL).
5.5 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature as a mask option. The
COP is implemented with an 18-bit ripple counter. This provides a
timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP
should time out, a system reset will occur and the device will be
re-initialized in the same fashion as a power-on reset (POR) or external
reset.
5.5.1 Resetting the COP
Preventing a COP reset is done by writing a logic 0 to the COPC bit. This
action will reset the counter and begin the timeout period again. The
COPC bit is bit 0 of address $1FF0. A read of address $1FF0 will result
in the user defined ROM data at that location.
5.5.2 COP During Wait Mode
The COP will continue to operate normally during wait mode. The
software should pull the device out of wait mode periodically and reset
the COP by writing to the COPC bit to prevent a COP reset.
5.5.3 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off
for the entire device. The COP counter will be reset when stop mode is
entered. If a reset is used to exit stop mode, the COP counter will be
reset after the 4064 cycles of delay after stop mode. If an interrupt is
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