MC68HC05B6
Rev. 4.1
Freescale
6-7
SERIAL COMMUNICATIONS INTERFACE
6
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros
for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start
edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in
Figure 6-4) are forced into the sample shift
register during the interval when detection of a start bit is anticipated (see
Figure 6-6); therefore,
the start bit will be accepted no sooner than it is anticipated.
Figure 6-4 SCI examples of start bit sampling technique
Figure 6-5 SCI sampling technique used on all bits
111
1
11
1
11
000
0
1RT 2RT 3RT
5RT
7RT
4RT
6RT
8RT
Start
qualifiers
Idle
Start edge
verification samples
16X internal sampling clock
RT clock edges for all three examples
Noise
Start
111
1
11
1
0
1
000
0
111
1
11
1
001
0
Start
Noise
RDI
<
Samples
Present bit
Next bit
Previous bit
16RT 1RT
8RT 9RT 10RT
16RT 1RT
RDI
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