MC68HC05B6
Rev. 4.1
Freescale
E-25
MC68HC705B16
14
E.7
A/D converter characteristics
Table E-9 A/D characteristics for 5V operation
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
(VRH = VDD and VRL = 0V)
—
± 0.5
LSB
Quantization error
Uncertainty due to converter resolution
—
± 0.5
LSB
Absolute accuracy
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
—
± 1LSB
Conversion range
Analog input voltage range
VRL
VRH
V
VRH
Maximum analog reference voltage
VRL
VDD + 0.1
V
VRL
Minimum analog reference voltage
VSS – 0.1
VRH
V
VR(1)
(1) Performance verified down to 2.5V VR, but accuracy is tested and guaranteed at VR = 5V±10%.
Minimum difference between VRH and VRL
3—
V
Conversion time
Total time to perform a single analog to digital conversion
a. External clock (OSC1, OSC2)
b. Internal RC oscillator
—
32
tCYC
s
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
GUARANTEED
Zero input reading
Conversion result when VIN = VRL
00
—
Hex
Full scale reading
Conversion result when VIN = VRH
—FF
Hex
Sample acquisition time Analog input acquisition sampling
a. External clock (OSC1, OSC2)
b. Internal RC oscillator(2)
(2) Source impedances greater than 10k will adversely affect internal charging time during input sampling.
—
12
tCYC
s
Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7
—
12
pF
Input leakage(3)
(3) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see
Figure 8-2).
Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH
—
1
A
