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| 型號(hào)： | MC68HC001EI12 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 148/189頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MPU 16BIT 12MHZ 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 12MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（25x25） |
| 包裝： | 管件 |
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MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
5- 15
bus request signal. When no acknowledge is received before the bus request signal is
negated, the processor continues the use of the bus.
5.2.2 Receiving The Bus Grant
The processor asserts BG as soon as possible. Normally, this process immediately follows
internal synchronization, except when the processor has made an internal decision to
execute the next bus cycle but has not yet asserted AS for that cycle. In this case, BG is
delayed until AS is asserted to indicate to external devices that a bus cycle is in progress.
BG can be routed through a daisy-chained network or through a specific priority-encoded
network. Any method of external arbitration that observes the protocol can be used.
5.2.3 Acknowledgment Of Mastership (3-Wire Bus Arbitration Only)
Upon receiving BG, the requesting device waits until AS, DTACK, and BGACK are negated
before asserting BGACK. The negation of AS indicates that the previous bus master has
completed its cycle. (No device is allowed to assume bus mastership while AS is
asserted.) The negation of BGACK indicates that the previous master has released the
bus. The negation of DTACK indicates that the previous slave has terminated the
connection to the previous master. (In some applications, DTACK might not be included in
this function; general-purpose devices would be connected using AS only.) When BGACK
is asserted, the asserting device is bus master until it negates BGACK. BGACK should not
be negated until after the bus cycle(s) is complete. A device relinquishes control of the bus
by negating BGACK.
The bus request from the granted device should be negated after BGACK is asserted. If
another bus request is pending, BG is reasserted within a few clocks, as described in 5.3
Bus Arbitration Control. The processor does not perform any external bus cycles before
reasserting BG.
5.3 BUS ARBITRATION CONTROL
All asynchronous bus arbitration signals to the processor are synchronized before being
used internally. As shown in Figure 5-17, synchronization requires a maximum of one
cycle of the system clock, assuming that the asynchronous input setup time (#47, defined
in Section 10 Electrical Characteristic) has been met. The input asynchronous signal is
sampled on the falling edge of the clock and is valid internally after the next falling edge.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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