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參數(shù)資料
| 型號： | MC68HC000FN10 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Addendum to M68000 User Manual |
| 中文描述： | 32-BIT, 10 MHz, MICROPROCESSOR, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 124K |
| 代理商： | MC68HC000FN10 |
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13
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued)
Applies to 3.3V and 5V.
NOTES:
1.
For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
2.
Actual value depends on clock period.
3.
If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
4.
For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the
system is powered up, #56 refers to the minimum pulse width required to reset the controller.
5.
If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
When AS and R/W are equally loaded (
±
20%), subtract 5 ns from the values given in these columns.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
6.
7.
NUM
CHARACTERISTIC
10MHz
MIN
0
—
0
—
16MHz
MIN
0
—
0
—
20MHz
MIN
0
—
0
—
UNIT
MAX
—
150
—
65
MAX
—
90
—
50
MAX
—
75
—
42
29
29A
30
31
2,5
32
33
34
35
36
7
38
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
AS, LDS, UDS Negated to Data-In High Impedance (Read)
AS, LDS, UDS Negated to BERR Negated
DTACK Asserted to Data-In Valid (Setup Time on Read)
ns
ns
ns
ns
HALT and RESET Input Transition Time
Clock High to BG Asserted
Clock High to BG Negated
BR Asserted to BG Asserted
BR Negated to BG Negated
0
—
—
1.5
1.5
150
35
35
3.5
3.5
0
—
—
1.5
1.5
150
30
30
3.5
3.5
0
—
—
1.5
1.5
150
25
25
3.5
3.5
ns
ns
ns
Clks
Clks
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
BG Width Negated
AS, LDS, UDS Negated to AVEC Negated
Asynchronous Input Setup Time
—
55
—
50
—
42
ns
39
44
47
5
48
2,3
52
53
55
56
4
58
7
58A
7
1.5
0
5
—
55
—
1.5
0
5
—
50
—
1.5
0
5
—
42
—
Clks
ns
ns
BERR Asserted to DTACK Asserted
20
—
10
—
10
—
ns
Data-In Hold from Clock High
Data-Out Hold from Clock High (Write)
R/W Asserted to Data Bus Impedance Change (Write)
HALT, RESET Pulse Width
0
0
20
10
—
—
—
—
0
0
10
10
—
—
—
—
0
0
0
—
—
—
—
ns
ns
ns
Clks
10
BR Negated to AS, LDS, UDS, R/W Driven
1.5
—
1.5
—
1.5
—
Clks
BR Negated to FC Driven
1
—
1
—
1
—
Clks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC000FN12 | Addendum to M68000 User Manual |
| MC68HC000FN16 | Addendum to M68000 User Manual |
| MC68HC000FN20 | Addendum to M68000 User Manual |
| MC68HC000FN8 | Addendum to M68000 User Manual |
| MC68HC000P10 | Addendum to M68000 User Manual |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC000FN12 | 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC68HC000FN16 | 功能描述:IC MPU 32BIT 16MHZ 68-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| MC68HC000FN16R2 | 功能描述:IC MPU 32BIT 16MHZ 68-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| MC68HC000FN20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Addendum to M68000 User Manual |
| MC68HC000FN8 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Addendum to M68000 User Manual |
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