參數(shù)資料
型號(hào): MC68EZ328ZC16V
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PBGA144
封裝: 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
文件頁(yè)數(shù): 121/246頁(yè)
文件大?。?/td> 2507K
代理商: MC68EZ328ZC16V
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MOTOROLA
MC68EZ328 USERS MANUAL
17-1
SECTION 17
APPLICATION GUIDE
This section contains information that will help you integrate the MC68EZ328 into your
design. It includes a design checklist and instructions for using the MC68EZ328 Application
Development System (ADS) board to get started with your design.
17.1 DESIGN CHECKLIST
When integrating the MC68EZ328 microprocessor into an application, the following items
can help guide you through the process. These guidelines originated from common
problems that were found while debugging and operating actual implementations.
Find the Mask Number and Version of Your Chip
Each chip has different sets of numbers etched onto it and one of these sets is the mask
and revision number for that particular chip. The mask number and the revision number
are combined into one. For example, 0F98S. 0 is the revision number and F98S is the
mask number. You need this information in order to find the errata for that version of
the chip. Obtaining the appropriate errata will help you design your product more
efficiently. Once you know your mask and revision numbers, go to our website and look
for your particular MC68EZ328 chip errata. If you do not have web access, contact your
local Motorola sales office.
Using the MC68EZ328 in a System With an 8-Bit Data Bus
To give you more flexibility, MC68EZ328 supports both 8- and 16-bit data bus modes.
You use the RESET and BUSW/DTACK/PG0 signals to select either 8- or 16-bit mode.
The default data bus width for the CSA0 and CSA1 signals is controlled by the BUSW
signal. CSA0 is normally connected to boot ROM. For a system with 16-bit data boot
ROM, BUSW is pulled high or left unconnected during system reset. For an 8-bit data
boot ROM system, BUWS must be externally driven low during system reset. The
BUSW status is latched by the rising edge of the RESET signal and the latched BUSW
status is indicated by the BUSW bit of the chip-select A control register. After reset, this
pin can be used as a DTACK or PG0 function.
After reset, BBUSW/DTACK/PG0 uses the DTACK function. You should permanently
drive this signal low for an 8-bit system to force all bus cycles to a zero wait-state until
this pin is reconfigured to the PG0 function. Fortunately, the system clock is divided by
two (the PRESC bit in the PLLCR register is set) after reset, which doubles the length
of each bus cycle and provides ample access time to memories. Therefore, you should
program the BUSW/DTACK/PG0 to the PG0 function before you configure the system
clock to divide by one (the PRESC bit in the PLLCR register is cleared).
相關(guān)PDF資料
PDF描述
MC68EZ328PU16V MICROPROCESSOR, PQFP100
MC68HC(9)08EB8MFA 8-BIT, 8.4 MHz, MICROCONTROLLER, PQFP32
MC68HC(9)08EB8VFA 8-BIT, 8.4 MHz, MICROCONTROLLER, PQFP32
MC68HC(9)08EB8CFN 8-BIT, 8.4 MHz, MICROCONTROLLER, PQCC44
MC68HC(9)08EB8VFN 8-BIT, 8.4 MHz, MICROCONTROLLER, PQCC44
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