Table of Contents
Paragraph
Number
9.8.1.11
9.8.1.12
9.8.1.13
9.8.1.14
9.8.2
9.8.2.1
9.8.2.2
9.8.2.3
9.8.2.4
9.8.2.5
9.8.2.6
9.8.3
9.8.3.1
9.8.3.2
9.8.4
9.8.5
9.9
Title
Page
Number
xxiv
MC68360 USER’S MANUAL
MOTOROLA
MC68EC030 Caching Configuration......................................................9-79
Double Bus Fault ...................................................................................9-79
JTAG and Three-State...........................................................................9-79
QUICC Serial Ports................................................................................9-79
Memory Interfaces.................................................................................9-79
QUICC Memory Interface Pins ..............................................................9-80
Regular EPROM or Flash EPROM........................................................9-80
Regular SRAM.......................................................................................9-82
EEPROM ...............................................................................................9-84
DRAM SIMM..........................................................................................9-84
DRAM Devices.......................................................................................9-86
Software Configuration ..........................................................................9-86
Basic Initialization ..................................................................................9-86
Configuring the Memory Controller........................................................9-87
Interfacing Multiple QUICCs to an MC68EC030....................................9-89
Using a Higher Speed MC68EC030 Master with the QUICC................9-89
Putting a Background Debug Mode Connector on a Target Board .......9-90
Section 10
Electrical Characteristics
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.9
10.9
10.9
10.10
10.11
tions
10.12
Maximum Ratings..................................................................................10-1
Thermal Characteristics.........................................................................10-2
Power Considerations............................................................................10-2
AC Electrical Specification Definitions...................................................10-3
DC Electrical Specifications...................................................................10-5
AC Power Dissipation............................................................................10-6
AC Electrical Specifications Control Timing...........................................10-7
External Capacitor for PLL.....................................................................10-8
Bus Operation AC Timing Specifications...............................................10-9
Bus Operation AC Timing Specifications (Continued).........................10-10
Bus Operation AC Timing Specifications (Continued)........................10-11
Bus Operation AC Timing Specifications (Continued ..........................10-12
Bus Operation—DRAM Accesses AC Timing Specifications .............10-28
030/QUICC Bus Type Slave Mode Bus Arbitration AC Electrical Specifica-
10-33
030/QUICC Bus Type Slave Mode Internal Read/Write/IACK
Asynchronous Cycles AC Electrical Specifications..............................10-36
030/QUICC Bus Type SRAM/DRAM Cycles AC Electrical Specifications10-
10.14
44
10.15
10.16
Specifications10-51
10.17
10.18
10.19
040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications10-49
040 Bus Type Slave Mode Internal Read/write/IACK Cycles AC Electrical
040 Bus Type SRAM/DRAM Cycles Ac Electrical Specifications.......10-56
IDMA AC Electrical Specifications......................................................10-62
PIP/PIO AC Electrical Specifications...................................................10-64