Serial Communication Controllers (SCCs)
MOTOROLA
MC68360 USER’S MANUAL
7-171
May Be Used with the SCC DPLL
Four Address Comparison Registers with Mask
Maintenance of Five 16-Bit Error Counters
Flag/Abort/Idle Generation/Detection
Zero Insertion/Deletion
16-Bit or 32-Bit CRC-CCITT Generation/Checking
Detection of Nonoctet Aligned Frames
Detection of Frames That Are Too Long
Programmable Flags (0–15) Between Successive Frames
Automatic Retransmission in Case of Collision
7.10.17.2 HDLC CHANNEL FRAME TRANSMISSION PROCESSING.
The HDLC trans-
mitter is designed to work with almost no intervention from the CPU32+ core. When the
CPU32+ core enables one of the transmitters, it will start transmitting flags or idles as pro-
grammed in the HDLC mode register. The HDLC controller will poll the first BD in the trans-
mit channel’s BD table. When there is a frame to transmit, the HDLC controller will fetch the
data from memory and start transmitting the frame (after first transmitting the user-specified
minimum number of flags between frames). When the end of the current BD has been
reached and the last buffer in the frame bit is set, the CRC, if selected, and the closing flag
are appended. In HDLC, the LSB of each octet is transmitted first, and the MSB of the CRC
is transmitted first. A typical HDLC frame is shown in Figure 7-50.
Figure 7-50. HDLC Framing Structure;
Following the transmission of the closing flag, the HDLC controller writes the frame status
bits into the BD and clears the R-bit. When the end of the current BD has been reached and
the last bit is not set (working in multibuffer mode), only the R-bit is cleared. In either mode,
an interrupt may be issued if the I-bit in the Tx BD is set. The HDLC controller will then pro-
ceed to the next Tx BD in the table. In this way, the user may be interrupted after each buffer,
after a specific buffer has been transmitted, or after each frame.
To rearrange the transmit queue before the CP has completed transmission of all buffers,
issue the STOP TRANSMIT command. This technique can be useful for transmitting expe-
dited data before previously linked buffers or for error situations. When receiving the STOP
TRANSMIT command, the HDLC controller will abort the current frame being transmitted
and start transmitting idles or flags. When the HDLC controller is given the RESTART
TRANSMIT command, it resumes transmission.
To insert a high-priority frame without aborting the current frame, the GRACEFUL STOP
TRANSMIT command may be issued. A special interrupt (GRA) can be generated in the
event register when the current frame is complete.
OPENING FLAG
ADDRESS
CONTROL
INFORMATION
(OPTIONAL)
CRC
CLOSING FLAG
8 BITS
16 BITS
8 BITS
8N BITS
16 BITS
8 BITS