Serial Interface with Time Slot Assigner
7-80
MC68360 USER’S MANUAL
MOTOROLA
RFSDx—Receive Frame Sync Delay for TDM A or B
These two bits determine the number of clock delays between the receive sync and the
first bit of the receive frame. Even if the CRTx bit is set, these bits do not control the delay
for the transmit frame.
00 = No bit delay (The first bit of the frame is transmitted/received on the same clock
as the sync; use for GCI.)
01 = 1-bit delay (Use for IDL.)
10 = 2-bit delay
11 = 3-bit delay
Refer to Figure 7-29 and Figure 7-30 for an example of the use of these bits.
DSCx—Double-Speed Clock for TDM A or B
Some TDMs such as GCI define the input clock to be 2
×
faster than the data rate. This bit
controls this option.
0 = The channel clock (L1RCLKx and/or L1TCLKx) is equal to the data clock. (Use for
IDL and most TDM formats.)
1 = The channel clock rate is twice the data rate. (Use for GCI.)
CRTx—Common Receive and Transmit Pins for TDM A or B
This bit is useful when the transmit and receive sections of a given TDM use the same
clock and sync signals. In this mode, L1TCLKx and L1TSYNCx pins can be used as gen-
eral-purpose I/O pins.
0 = Separate pins. The receive section of this TDM uses L1RCLKx and L1RSYNCx
pins for framing, and the transmit section uses L1TCLKx and L1TSYNCx for fram-
ing.
1 = Common pins. The receive and transmit sections of this TDM use L1RCLKx as
clock pin of channel x and L1RSYNCx as the receive and transmit sync pin. (Use
for IDL and GCI.)
STZx—Set L1TXDx to Zero for TDM A or B
0 = Normal operation.
1 = L1TXDx is set to zero until serial clocks are available, which is useful for GCI acti-
vation. Refer to 7.8.7.1 SI GCI Activation/Deactivation Procedure.
CEx—Clock Edge for TDM A or B
When DSCx =0
0 = The data is transmitted on the rising edge of the clock and received on the falling
edge. (Use for IDL and GCI.)
1 = The data is transmitted on the falling edge of the clock and received on the rising
edge.
When DSCx = 1
0 = The data is transmitted on the rising edge of the clock and received on the rising
edge. (Use for IDL and GCI.)
1 = The data is transmitted on the falling edge of the clock and received on the falling
edge.