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參數(shù)資料
| 型號： | MC68EC060 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessors.(32位微處理器) |
| 中文描述： | 32位微處理器。（32位微處理器） |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 68K |
| 代理商： | MC68EC060 |
6
MC68060 PRODUCT INFORMATION
MOTOROLA
The integer unit control logic pulls an instruction pair from the instruction buffer every machine clock cycle,
stopping only if the instruction information is not available or if an integer execution pipeline hold condition ex-
ists. The six stages in the dual integer execution pipelines are:
1)
Instruction Decode—The instruction is fully decoded.
2)
Effective Address Calculation—If the instruction calls for data from memory, the location of the data is
calculated.
3)
Effective Address Fetch—Data is fetched from the memory location.
4)
Integer Execution—The data is manipulated during execution.
5)
Data Available—The result is available.
6)
Write-Back—The resulting data is written back to on-chip caches or external memory.
The MC68060 is optimized for most integer instructions to execute in one machine clock cycle. If during the
instruction decode stage the instruction is determined to be a floating-point instruction, it will be passed to the
FPU after the effective address fetch stage. If data is to be written to either the on-chip caches or external
memory after instruction execution, the write-back stage holds the data until memory is ready to receive it.
Temporarily holding data in the write-back stage adds to the overall performance of the MC68060 by not
slowing down pipeline operations.
The MC68060 implements practically all of the MC68040 instructions and addressing modes in hardware for
the highest performance. However, to optimize silicon usage, a very few infrequently used integer instructions
are not fully implemented in hardware. These instructions are emulated in software using the M68060SP which
is available free from Motorola. This software package assures full binary compatibility. Since these
instructions appear very infrequently in the instruction stream, software emulation of the instructions provides
no noticeable loss in performance.
FLOATING-POINT UNIT
(MC68060 ONLY)
Floating-point math is distinguished from integer math, which deals only with whole numbers and fixed decimal
point locations. The IEEE-compatible MC68060 FPU computes numeric calculations with a variable decimal
point location. The MC68060 features a built-in FPU that is MC68040 and MC68881/882 compatible.
Consolidating this important function on-chip speeds up overall processing and eliminates the interfacing
overhead associated with external accelerators. The MC68060 FPU operates in parallel with the integer unit.
The FPU performs numeric calculations while the integer unit continues integer processing.
The FPU has been optimized for the most frequently used instructions and data types to provide the highest
possible performance. The FPU can also be disabled in software to reduce system power consumption.
The MC68060 implements the most frequently used M68000 family floating-point instructions, data types, and
data formats in hardware for the highest performance. The remaining instructions are emulated in software
with the M68060SP to provide complete IEEE compatibility. The M68060SP provides the following features:
Arithmetic and Transcendental Instructions
IEEE-Compliant Exception Handlers
Unimplemented Data Type and Data Format Handlers
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