參數(shù)資料
型號(hào)： MC68B912B32FU8
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-Bit Microcontroller
中文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 39/128頁
文件大?。?/td> 748K
代理商： MC68B912B32FU8
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
39
STRE — Spare Test Row Enable
The spare test row consists of one Flash EEPROM array row. The reserved word at location 31 contains
production test information which must be maintained through several erase cycles. When STRE is set,
the decoding for the spare test row overrides the address lines which normally select the other rows in
the array.
0 = LIB accesses are to the Flash EEPROM array
1 = Spare test row in array enabled if SMOD is active
MWPR — Multiple Word Programming
Used primarily for testing, if MPWR = 1, the two least-significant address lines ADDR[1:0] will be ignored
when programming a Flash EEPROM location. The word location addressed if ADDR[1:0] = 00, along
with the word location addressed if ADDR[1:0] = 10, will both be programmed with the same word data
from the programming latches. This bit should not be changed during programming.
0 = Multiple word programming disabled
1 = Program 32 bits of data
This register controls the programming and erasure of the Flash EEPROM.
FEESWAI — Flash EEPROM Stop in Wait Control
0 = Do not halt Flash EEPROM clock when the part is in wait mode.
1 = Halt Flash EEPROM clock when the part is in wait mode.
NOTE
The FEESWAI bit cannot be asserted if the interrupt vector resides in theFlash
EEPROM array.
SVFP — Status V
FP
Voltage
SVFP is a read only bit.
0 = Voltage of V
FP
pin is below normal programming voltage levels
1 = Voltage of V
FP
pin is above normal programming voltage levels
ERAS — Erase Control
This bit can be read anytime or written when ENPE = 0. When set, all locations in the array will be
erased at the same time. The boot block will be erased only if BOOTP = 0. This bit also affects the result
of attempted array reads. See
Table 14
for more information. Status of ERAS cannot change if ENPE
is set.
0 = Flash EEPROM configured for programming
1 = Flash EEPROM configured for erasure
LAT — Latch Control
This bit can be read anytime or written when ENPE = 0. When set, the Flash EEPROM is configured
for programming or erasure and, upon the next valid write to the array, the address and data will be
latched for the programming sequence. See
Table 14
for the effects of LAT on array reads. A high volt-
age detect circuit on the V
FP
pin will prevent assertion of the LAT bit when the programming voltage is
at normal levels.
0 = Programming latches disabled
1 = Programming latches enabled
FEECTL
— Flash EEPROM Control Register
$00F7
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
FEESWAI
SVFP
ERAS
LAT
ENPE
RESET:
0
0
0
0
0
0
0
0
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