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參數(shù)資料
| 型號： | MC68B912B32FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 127/128頁 |
| 文件大?。?/td> | 748K |
| 代理商： | MC68B912B32FU8 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
127
16.4 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be reconstructed in real time or from trace
history that was captured by a logic analyzer. However, the reconstructed queue cannot be used to stop
the CPU at a specific instruction, because execution has already begun by the time an operation is vis-
ible outside the MCU. A separate instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for tagging. Tagging information is
latched on the falling edge of ECLK along with program information as it is fetched. Tagging is allowed
in all modes. Tagging is disabled when BDM becomes active and BDM serial commands cannot be pro-
cessed while tagging is active.
TAGHI is a shared function of the BKGD pin.
TAGLO is a shared function of the PE3/LSTRB pin, a multiplexed I/O pin. For 1/4 cycle before and after
the rising edge of the E clock, this pin is the LSTRB driven output.
TAGLO and TAGHI inputs are captured at the falling edge of the E clock. A logic zero on TAGHI and/or
TAGLO marks (tags) the instruction on the high and/or low byte of the program word that was on the
data bus at the same falling edge of the E clock.
The tag follows the information in the queue as the queue is advanced. When a tagged instruction
reaches the head of the queue, the CPU enters active background debugging mode rather than exe-
cuting the instruction. This is the mechanism by which a development system initiates hardware break-
points.
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