MC68336/376
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
8-2
8.2 QADC Address Map
The QADC occupies 512 bytes of address space. Nine words are control, port, and
status registers, 40 words are the CCW table, and 120 words are the result word table
because 40 result registers can be read in three data alignment formats. The remain-
ing words are reserved for expansion. Refer to D.5 QADC Module for information
concerning the QADC address map.
8.3 QADC Registers
The QADC has three global registers for configuring module operation: the module
configuration register (QADCMCR), the interrupt register (QADCINT), and a test reg-
ister (QADCTEST). The global registers are always defined to be in supervisor data
space. The CPU32 allows software to establish the global registers in supervisor data
space and the remaining registers and tables in user space.
All QADC analog channel/port pins that are not used for analog input channels can be
used as digital port pins. Port values are read/written by accessing the port A and B
data registers (PORTQA and PORTQB). Port A pins are specified as inputs or outputs
by programming the port data direction register (DDRQA). Port B is an input only port.
The four remaining control registers configure the operation of the queuing mecha-
nism, and provide a means of monitoring the operation of the QADC. Control register
0 (QACR0) contains hardware configuration information. Control register 1 (QACR1)
is associated with queue 1, and control register 2 (QACR2) is associated with queue
2. The status register (QASR) provides visibility on the status of each queue and the
particular conversion that is in progress.
Following the register block in the address map is the CCW table. There are 40 words
to hold the desired analog conversion sequences. Each CCW is a 16-bit word, with ten
for more information.
The final block of address space belongs to the result word table, which appears in
three places in the memory map. Each result word table location holds one 10-bit con-
version value. The software selects one of three data formats, which map the 10-bit
result onto the 16-bit data bus by reading the address which produces the desired
alignment. The first address block presents the result data in right justified format, the
second block is presented in left justified signed format, and the third is presented in
8.4 QADC Pin Functions
The QADC uses a maximum of 21 external pins. There are 16 channel/port pins that
can support up to 41 channels when external multiplexing is used (including internal
channels). All of the channel pins can also be used as general-purpose digital port
pins.
In addition, there are also two analog reference pins, two analog submodule power
pins, and one VSS pin for the open drain output drivers on port A.