MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
5-22
The supervisor bit in the status register determines whether the CPU is operating in
supervisor or user mode. Addressing mode and the instruction being executed deter-
mine whether a memory access is to program or data space.
5.5.1.8 Data and Size Acknowledge Signals
During normal bus transfers, external devices assert the data and size acknowledge
signals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these sig-
nals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the
signals indicate that an external device has successfully stored data and that the cycle
can terminate. DSACK[1:0] can also be supplied internally by chip-select logic. Refer
5.5.1.9 Bus Error Signal
The bus error signal (BERR) is asserted when a bus cycle is not properly terminated
by DSACK or AVEC assertion. It can also be asserted in conjunction with DSACK to
indicate a bus error condition, provided it meets the appropriate timing requirements.
The internal bus monitor can generate the BERR signal for internal-to-internal and
internal-to-external transfers. In systems with an external bus master, the SIM bus
monitor must be disabled and external logic must be provided to drive the BERR pin,
because the internal BERR monitor has no information about transfers initiated by an
5.5.1.10 Halt Signal
The halt signal (HALT) can be asserted by an external device for debugging purposes
to cause single bus cycle operation or (in combination with BERR) a retry of a bus
cycle in error. The HALT signal affects external bus cycles only. As a result, a program
not requiring use of the external bus may continue executing, unaffected by the HALT
signal.
When the MCU completes a bus cycle with the HALT signal asserted, DATA[15:0] is
placed in a high-impedance state and bus control signals are driven inactive; the
address, function code, size, and read/write signals remain in the same state. If HALT
is still asserted once bus mastership is returned to the MCU, the address, function
code, size, and read/write signals are again driven to their previous states. The MCU
5.5.1.11 Autovector Signal
The autovector signal (AVEC) can be used to terminate external interrupt acknowl-
edge cycles. Assertion of AVEC causes the CPU32 to generate vector numbers to
locate an interrupt handler routine. If AVEC is continuously asserted, autovectors are
generated for all external interrupt requests. AVEC is ignored during all other bus
cycles. Refer to 5.8 Interrupts for more information. AVEC for external interrupt
requests can also be supplied internally by chip-select logic. Refer to 5.9 Chip-