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參數資料
| 型號： | MC68341 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Integrated Processor Users Manual |
| 中文描述： | 綜合處理器用戶手冊 |
| 文件頁數： | 2/21頁 |
| 文件大?。?/td> | 134K |
| 代理商： | MC68341 |
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MC68341UMAD/AD
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
ADDENDUM TO
MC68341 Integrated Processor User's Manual
MC68341
MOTOROLA, 1995
Microprocessor and Memory
Technologies Group
SEMICONDUCTOR PRODUCT INFORMATION
April 19, 1995
This addendum to the initial release of the MC68341UM/AD User’s Manual provides corrections to the original
text, plus additional information not included in the original. This document and other information on this product
is maintained on the AESOP BBS, which can be reached at (800)843-3451 (from the US and Canada) or
(512)891-3650. Configure modem for up to 14.4Kbaud, 8 bits, 1 stop bit, and no parity. Terminal software
should support VT100 emulation. Internet access is provided by telneting to pirs.aus.sps.mot.com
[129.38.233.1] or through the World Wide Web at http://pirs.aus.sps.mot.com.
1. Signal Index
On page 2-4, Table 2-4, the QSPI serial clock QSCLK should be listed as an I/O signal. At the bottom of Table
2-5, FC3/DTC is an output-only signal.
2. Operand Alignment
On page 3-9, last paragraph, change the first two lines to: “The CPU32 restricts all operands (both data and
instructions) to be word-aligned. That is, word and long-word operands must be located on a word boundary.”
Long-word operands do not have to be long-word aligned.
3. WE on Fast Termination
On page 3-17, Figure 3-6, UWE and LWE do not assert for fast termination writes.
4. Write Cycle Timing Waveforms
On page 3-25, the M68300 write cycle timing diagram (Figure 3-12) shows incorrect timing for DS, UWE, and
LWE. On page 3-28, the M68000 write cycle timing diagram (Figure 3-14) shows incorrect timing for AS68K,
CSx, UDS/LDS, and UWE/LWE. Replace these figures with the following corrected figures.
5. Additional Note on MBAR Decode
Add to the CPU Space Cycles description on page 3-31: The CPU space decode logic allocates the 256-byte
block from $3FF00-3FFFF to the SIM module. An internal 2-clock termination is provided by this initial decode
for any access to this range, but selection of specific registers depends on additional decode.
Accesses to the MBAR register at long word $3FF00 are internal only, and are only visible by enabling show
cycles. Users should directly access only the MBAR register, and use the LPSTOP instruction to generate the
LPSTOP broadcast access to $3FFFE. The remaining address range $3FF04-3FFFD is Motorola reserved and
should not be accessed.
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