參數(shù)資料
型號(hào)： MC68334GCFC20
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 20 MHz, MICROCONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁(yè)數(shù)： 16/76頁(yè)
文件大小： 444K
代理商： MC68334GCFC20
MC68334
MOTOROLA
MC68334TS/D REV. 1
23
mum limp frequency does not exceed one half maximum system clock when X = 0, or maximum
system clock frequency when X = 1.
When RSTEN is set, the SIM resets the MCU.
The limp status bit (SLIMP) in SYNCR indicates whether the synthesizer has a reference signal. It is set
when a reference failure is detected.
3.3.6 Clock Control
The clock control circuits determine system clock frequency and clock operation under special circum-
stances, such as following loss of synthesizer reference or during low-power operation. Clock source is
determined by the logic state of the MODCLK pin during reset.
When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper
byte of SYNCR. Bits in the lower byte show status of or control operation of internal and external clocks.
The SYNCR can be read or written only when the CPU is operating at the supervisor privilege level.
W — Frequency Control (VCO)
This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO
speed by a factor of four. VCO relock delay is required.
X — Frequency Control Bit (Prescale)
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting the bit
doubles clock speed without changing the VCO speed. There is no VCO relock delay.
Y[5:0] — Frequency Control (Counter)
The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by
a value of Y
+ 1. Values range from 0 to 63. VCO relock delay is required.
EDIV — E Clock Divide Rate
0 = ECLK frequency is system clock divided by 8.
1 = ECLK frequency is system clock divided by 16.
ECLK is an external M6800 bus clock available on pin ADDR23. Refer to 3.5 Chip Selects for more
information.
SLIMP — Limp Mode Flag
0 = External crystal is VCO reference.
1 = Loss of crystal reference.
When the on-chip synthesizer is used, loss of reference frequency causes SLIMP to be set. The VCO
continues to run using the base control voltage. Maximum limp frequency is maximum specified system
clock frequency. X-bit state affects limp frequency.
SLOCK — Synthesizer Lock Flag
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency (or system clock is external).
The MCU maintains reset state until the synthesizer locks, but SLOCK does not indicate synthesizer
lock status until after the user writes to SYNCR.
SYNCR — Clock Synthesizer Control Register
$YFFA04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
X
Y
EDIV
0
SLIMP
SLOCK
RSTEN
STSIM
STEXT
RESET:
0
1
0
U
0
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