• 參數(shù)資料
    型號(hào): MC68332TS
    廠商: Motorola, Inc.
    英文描述: 32-Bit Modular Microcontroller
    中文描述: 32位微控制器模塊
    文件頁(yè)數(shù): 72/88頁(yè)
    文件大?。?/td> 446K
    代理商: MC68332TS
    MOTOROLA
    72
    MC68332
    MC68332TS/D
    6.5.2 QSPI Registers
    The programmer's model for the QSPI submodule consists of the QSM global and pin control registers,
    four QSPI control registers, one status register, and the 80-byte QSPI RAM.
    The CPU can read and write to registers and RAM. The four control registers must be initialized before
    the QSPI is enabled to ensure defined operation. SPCR1 should be written last because it contains
    QSPI enable bit SPE. Asserting this bit starts the QSPI. The QSPI control registers are reset to a de-
    fined state and can then be changed by the CPU. Reset values are shown below each register.
    Refer to the following memory map of the QSPI.
    Writing a different value into any control register except SPCR2 while the QSPI is enabled disrupts op-
    eration. SPCR2 is buffered to prevent disruption of the current serial transfer. After completion of the
    current serial transfer, the new SPCR2 values become effective.
    Writing the same value into any control register except SPCR2 while the QSPI is enabled has no effect
    on QSPI operation. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location.
    SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write
    this register. The QSM has read-only access.
    Pin Names
    Mnemonics
    MISO
    Mode
    Master
    Slave
    Master
    Slave
    Master
    Slave
    Master
    Master
    Master
    Slave
    Function
    Master In Slave Out
    Serial Data Input to QSPI
    Serial Data Output from QSPI
    Serial Data Output from QSPI
    Serial Data Input to QSPI
    Clock Output from QSPI
    Clock Input to QSPI
    Select Peripherals
    Selects Peripheral
    Causes Mode Fault
    Initiates Serial Transfer
    Master Out Slave In
    MOSI
    Serial Clock
    SCK
    Peripheral Chip Selects
    Peripheral Chip Select
    Slave Select
    PCS[3:1]
    PCS0
    SS
    Address
    $YFFC18
    $YFFC1A
    $YFFC1C
    $YFFC1E
    $YFFC1F
    $YFFD00
    $YFFD20
    $YFFD40
    Name
    SPCR0
    SPCR1
    SPCR2
    SPCR3
    SPSR
    RAM
    RAM
    RAM
    Usage
    QSPI Control Register 0
    QSPI Control Register 1
    QSPI Control Register 2
    QSPI Control Register 3
    QSPI Status Register
    QSPI Receive Data (16 Words)
    QSPI Transmit Data (16 Words)
    QSPI Command Control (8 Words)
    SPCR0
    — QSPI Control Register 0
    $YFFC18
    15
    14
    13
    10
    9
    8
    7
    0
    MSTR
    WOMQ
    BITS
    CPOL
    CPHA
    SPBR
    RESET:
    0
    0
    0
    0
    0
    0
    0
    1
    0
    0
    0
    0
    0
    1
    0
    0
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