MOTOROLA
5-14
CENTRAL PROCESSING UNIT
MC68331
USER’S MANUAL
5
NOTE:
1. Privileged instruction
5.8.1 M68000 Family Compatibility
It is the philosophy of the M68000 family that all user-mode programs can execute un-
changed on a more advanced processor, and supervisor-mode programs and excep-
tion handlers should require only minimal alteration.
The CPU32 can be thought of as an intermediate member of the M68000 Family. Ob-
ject code from an MC68000 or MC68010 may be executed on the CPU32, and many
of the instruction and addressing mode extensions of the MC68020 are also support-
ed. Refer to the CPU32 reference manual for a detailed comparison of the CPU32 and
MC68020 instruction set.
5.8.2 Special Control Instructions
Low power stop (LPSTOP) and table lookup and interpolate (TBL) instructions have
been added to the MC68000 instruction set for use in controller applications.
5.8.2.1 Low Power Stop (LPSTOP)
In applications where power consumption is a consideration, the CPU32 forces the de-
vice into a low power standby mode when immediate processing is not required. The
low power stop mode is entered by executing the LPSTOP instruction. The processor
remains in this mode until a user-specified (or higher) interrupt level or reset occurs.
5.8.2.2 Table Lookup and Interpolate (TBL)
To maximize throughput for real-time applications, reference data is often precalculat-
ed and stored in memory for quick access. Storage of many data points can require
an inordinate amount of memory. The table instruction requires that only a sample of
data points be stored, reducing memory requirements. The TBL instruction recovers
intermediate values using linear interpolation. Results can be rounded with a round-
to-nearest algorithm.
5.9 Exception Processing
Exception processing is a special condition that preempts normal processing. Excep-
tion processing is the transition from normal mode program execution to execution of
a routine that deals with an exception.
TRAPcc
none
#<data>
none
<ea>
An
none
16, 32
none
8, 16, 32
32
If cc true, then TRAP exception
TRAPV
TST
UNLK
If V set, then overflow TRAP exception
Source – 0, to set condition codes
An
SP; (SP)
An, SP + 4
SP
Table 5-1 Instruction Set Summary (Continued)
Instruction
Syntax
Operand Size
Operation