
M-Bus Interface Module
7-8
MC68307 USER’S MANUAL
MOTOROLA
MIEN—M-Bus Interrupt Enable
1 = Interrupts from the M-bus module are enabled. An M-bus interrupt occurs provided
the MIF bit in the status register is also set.
0 = Interrupts from the M-bus module are disabled. Note that this does not clear any
currently pending interrupt condition.
MSTA—Master/Slave Mode Select Bit
Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is
generated on the bus, and the master mode is selected. When this bit is cleared, a STOP
signal is generated and the operation mode changes from master to slave.
MSTA is cleared without generating a STOP signal when the master loses arbitration.
1 = Master mode
0 = Slave mode
MTX—Transmit/Receive Mode Select Bit
This bit selects the direction of master and slave transfers. When addressed as a slave
this bit should be set by software according to the SRW bit in the status register. In master
mode this bit should be set according to the type of transfer required. Hence for address
cycles this bit is always high.
1 = Transmit
0 = Receive
TXAK—Transmit Acknowledge Enable
This bit specifies the value driven onto SDA during acknowledge cycles for both master
and slave receivers.
1 = No acknowledge signal response is sent (i.e., acknowledge bit = 1)
0 = An acknowledge signal is sent out to the bus at the 9th clock bit after receiving one
byte data.
RSTA—Repeat Start
Writing a 1 to this bit generates a repeated START condition on the bus, provided we are
the current bus master. This bit is always read as a low. Attempting a repeated start at the
wrong time, if the bus is owned by another master, results in loss of arbitration.
1 = Generate repeat start cycle.
0 = Do not generate repeat start cycle.
Bits 1–0—Reserved by Motorola.