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參數(shù)資料
| 型號： | MC68307FG |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 354K |
| 代理商： | MC68307FG |
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MOTOROLA
MC68307 TECHNICAL INFORMATION
15
UART MODULE
The UART module in the MC68307 is based on the MC68681 DUART, which is part of the M68000 family of
peripherals which directly interfaces to the MC68000 processor via an asynchronous bus structure. The UART
module consists of internal control logic, timing and baud-rate generator logic, interrupt control logic, and the
serial communications channel. Only one serial channel is implemented for the MC68307.
Clocking is provided by the MC68307 system clock, via a programmable prescaler. This allows various baud
rates to be chosen. Modem support is provided with request-to-send (RTS) and clear-to-send (CTS) signals
available. The serial port can sustain data rates of 5Mbits/s.
The features of the UART include:
Full-duplex asynchronous/synchronous receiver/transmitter channels
Maximum data transfer: 1X clock—5 Mbits/s, 16X clock—625 Kbits/s
Quadruple-buffered receiver data registers
Double-buffered transmitter data registers
Programmable baud rate for serial channel
— User defined rate derived from a programmable timer
Programmable data format
— Five to eight data bits plus parity
— Odd, even, no parity, or force parity
— One, one and one-half, or two stop bits programmable in 1/16 bit increments
Programmable channel modes for diagnostics
— Normal (full duplex)/automatic echo/local loopback/remote loopback
Automatic wake-up mode for multidrop applications
Versatile interrupt system
— Single interrupt output with eight maskable interrupting conditions
— Interrupt vector output on interrupt acknowledge
Parity, framing, and overrun error detection
False-start bit detection
Line-break detection and generation
Detects break which originates in the middle of a character
Interrupt or poll on start/stop break
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