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參數(shù)資料
| 型號： | MC68307FG16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 58/264頁 |
| 文件大?。?/td> | 949K |
| 代理商： | MC68307FG16 |
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M-Bus Interface Module
7-4
MC68307 USER’S MANUAL
MOTOROLA
edge bit, which is signalled from the receiving device by pulling the SDA low at the 9th clock.
So one complete data byte transfer needs 9 clock pulses.
If the slave receiver does not acknowledge the master, the SDA line must be left high by the
slave. The master can then generate a stop signal to abort the data transfer or a start signal
(repeated start) to commence a new calling.
If the master receiver does not acknowledge the slave transmitter after a byte transmission,
it means 'end of data' to the slave, so that the slave should release the SDA line for the mas-
ter to generate STOP or START signal.
7.2.4 Repeated START Signal
As shown in Figure 7-2, a repeated START signal is to generate a START signal without
first generating a STOP signal to terminate the communication. This is used by the master
to communicate with another slave or with the same slave in different mode (transmit/
receive mode) without releasing the bus.
7.2.5 STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus.
However, the master may generate a START signal followed by a calling command without
generating a STOP signal first. This is called repeated START. A STOP signal is defined as
a low-to-high transition of SDA while SCL at logical high. (Refer to Figure 7-2).
7.2.6 Arbitration Procedure
M-bus is a true multi-master bus that allows more than one master to be connected on it. If
two or more masters try to control the bus at the same time, a clock synchronization proce-
dure determines the bus clock, for which the low period is equal to the longest clock low
period and the high is equal to the shortest one among the masters. The relative priority of
the contending masters is determined by a data arbitration procedure, a bus master loses
arbitration if it transmits logic “1” while another master transmits logic “0”. The losing masters
immediately switch over to slave receive mode and stop driving SDA output. In this case the
transition from master to slave mode does not generate a STOP condition. Meanwhile, a
status bit is set by hardware to indicate lost of arbitration.
7.2.7 Clock Synchronization
Since wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects
all the devices connected on the bus. The devices start counting their low period and once
a device's clock has gone low, it holds the SCL line low until the clock high state is reached.
However, the change from low to high in this device clock may not change the state of the
SCL line if another device clock is still within its low period. Therefore, synchronized clock
SCL is held low by the device with the longest low period. Devices with shorter low periods
enter a high wait state during this time (Refer to Figure 7-3). When all devices concerned
have counted off their low period, the synchronized clock SCL line is released and is pulled
high. There is then no difference between the device clocks and the state of the SCL line
and all the devices start counting their high periods. The first device to complete its high
period pulls the SCL line low again.
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| MC68307UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
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