參數(shù)資料
型號: MC68302PV33C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù): 60/128頁
文件大?。?/td> 641K
代理商: MC68302PV33C
MC68EN302 DRAM Control Module
3-6
MC68EN302 REFERENCE MANUAL
MOTOROLA
Figure 3-3. Precharge With DRAM Access Active
3.8 DRAM CONTROLLER I/O
3.8.1 Control Signal Pins
The EN302 contains 8 DRAM specific signal pins: CAS1–CAS0, RAS1–RAS0, AMUX, and
DRAMRW.
3.8.2 Column Address Strobes (CAS1–CAS0)
These active low pins allow seamless interface to column address strobe (CAS) inputs on
industry standard DRAM, providing CAS for both bank 0 and bank 1 of the DRAM controller.
Two strobes support byte operations on the external 16-bit bus. CAS0 corresponds to data
pins D15-D8. CAS1 corresponds to data pins D7–D0.
3.8.3 Row Address Strobes (RAS1–RAS0)
These active low pins allow seamless interface to row address strobe (RAS) inputs on
industry standard DRAM, providing RAS for both bytes of a given DRAM bank. A particular
bank corresponds to specific base address and control information programmed in the
MC68EN302 DRAM control registers (see 3.2 Memory Map for a description). RAS0
corresponds to bank 0 and RAS1 corresponds to Bank 1.
3.8.4 DRAM Read/Write (DRAMRW)
This active low pin is asserted to signify that a DRAM write cycle is occurring. It is separate
from the processor bus R/W so that precharge takes place without regard to the state of R/
W.
S2 S3 S4
W
S1
CLOCK
S0
W
ADDR
RAS
CAS
DRAMRW
AS
UDS/LDS
S5 S6 S7
AMUX
WWWWWWW
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