參數(shù)資料
型號: MC68302PV33C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù): 115/128頁
文件大?。?/td> 641K
代理商: MC68302PV33C
IEEE 1149.1 (JTAG) Test Access Port
7-2
MOTOROLA
TDO—a three-stateable test data output that is actively driven in the shift-IR and shift-
DR controller states. TDO changes on the falling edge of TCK.
TRST—an asynchronous reset (with an internal pullup resistor) that provides initializa-
tion of the TAP controller and other logic required by the standard.
Figure 7-1. Test Logic Block Diagram
7.2 TAP CONTROLLER
The TAP controller is responsible for interpreting the sequence of logical values on the TMS
signal. It is a synchronous state machine that controls the operation of the JTAG logic. The
state machine is shown in Figure 7-2. The value shown adjacent to each arc represents the
value of the TMS signal sampled on the rising edge of the TCK signal. For a description of
the TAP controller states, refer to the IEEE 1149.1 document.
BOUNDARY SCAN REGISTER
BYPASS
DECODER
TDO
TDI
TMS
TCK
TRST
0
1
2
0
195
M
U
X
M
U
X
3-BIT INSTRUCTION REGISTER
TAP
CTLR
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