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參數(shù)資料
| 型號： | MC68150FN33 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 4/40頁 |
| 文件大小： | 384K |
| 代理商： | MC68150FN33 |
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ASYNCHRONOUS
OPERA
TION
ONL
Y
MC68150
12
MOTOROLA
High Performance Frequency
Control Products — BR1334
AC SPECIFICATIONS (VCC = 5.0V ±10%; TA = –40°C to +85°C; CL = 50pF; RL = 500)
Spec
25MHz
33MHz
40MHz
Spec
Number
Specification/Characteristic
Min
Max
Min
Max
Min
Max
Unit
1
CS Asserted to BCLK Rising (Setup)
5
4
ns
2
BCLK Rising to CS Negated (Hold)
2
1
ns
3
A1, A0, SIZ1, SIZ0, R/W Valid to BCLK Falling (Setup)
8
ns
4
BCLK Rising to A1, A0, SIZ1, SIZ0, R/W Invalid (Hold)
0
ns
5
D31:0 Valid to BCLK Rising [WRITE] (Setup)
3
2
1
ns
6
BCLK Rising to D31:0 Invalid [WRITE] (Hold)
0
ns
7
BCLK Rising to PA1, PA0 Valid (tPLH, tPHL)
2
12.5
2
10
2
9
ns
8
BCLK Rising to PA1, PA0 Invalid (tPLH, tPHL)
2
22
2
21
2
20
ns
9
PD31:16 Valid to BLCK Falling [READ] (Setup)
2
ns
10
BCLK Falling to PD31:16 Invalid [READ] (Hold)
8
6
5.5
ns
11
DSACK1, DSACK0 Valid to BCLK Falling (Setup)
4
2
ns
12
BCLK Falling to DSACK1, DSACK0 Invalid (Hold)
8
6
5
ns
13
BCLK Falling to DS, SWE, UWE, LWE (tPLH, tPHL)
3
10
3
9
3
9
ns
14
BCLK Rising to TA (tPLH, tPHL)
2
13
2
10
2
9
ns
15
BCLK Rising D31:16 Low Impedance [READ] (tPZL, tPZH)
2
16
2
15
2
14
ns
16
BCLK Rising to D15:0 Low Impedance [READ] (tPZL, tPZH)
2
16
2
15
2
14
ns
17
BCLK Rising to D31:0 Valid [READ] (tPLH, tPHL)
0
3
0
2
0
1
ns
18a
BCLK Rising to D31:16 High Impedance [READ] (tPLZ, tPHZ)
4
18
4
16
3
14
ns
18b
BCLK Rising to D15:0 High Impedance [READ] (tPLZ, tPHZ)
4
22
4
20
3
19
ns
19
BCLK Rising to PD31:16 Valid [WRITE] (tPZL, tPZH)
2
23
2
22
2
21
ns
20
BCLK Rising to PD31:16 [WRITE] (tPLH, tPHL)
4
17
4
16
3
15
ns
21
BCLK Rising to PD31:16 High Impedance [WRITE] (tPLZ, tPHZ)
3
19
3
18
3
17
ns
22
DS Asserted to SWE, UWE, LWE Asserted [WRITE] (Skew)
±0.5
ns
23
DS Negated to SWE, UWE, LWE Negated [WRITE] (Skew)
±1.0
ns
24
DSACK1, DSACK0, Invalid to DS Negated (tPLH)
4
ns
25
DS Negated Width
38
42
28
32
23
27
ns
26
SWE, UWE, LWE Negated Width
38
42
28
32
23
27
ns
27
CS to DSACK1, DSACK0 Valid
23
21
20
ns
28
PD31:16 Valid to DS, SWE, UWE, LWE Asserted [WRITE]
23
22
21
ns
29
SWE, LWE, UWE Negated to PD31:16 Invalid [WRITE]
27
26
25
ns
30
DS Negated to PD31:16 High Impedance [WRITE]
27
26
25
ns
31
DS Negated to PD31:16 Invalid [READ]
3
2
ns
32
DS, SWE, UWE, LWE Asserted Width
38
42
28
32
23
27
ns
33a
CS Negated to D31:16 High Impedance [READ] (tPHZ, tPLZ)
15
75
15
55
15
45
ns
33b
CS Negated to D15:0 High Impedance [READ] (tPHZ, tPLZ)
20
70
20
50
20
40
ns
34
PD31:16 Valid to DS Negated [READ]
8
ns
35
CS Negated to BCLK Rising (Setup) Guarantees Sync Termination
3
ns
36
BCLK Rising to CS Negated (Hold) Guarantees Async Termination
4
ns
37a
TA Negation to D31:16 High Impedance [READ] (Async Termination)
11
10
9
ns
37b
TA Negation to D15:0 High Impedance [READ] (Async Termination)
13
12
11
ns
38
CS Negated to TA Negated (Asynchronous Termination)
2
10
2
9
2
8.5
ns
39a
CS Negated to D31:16 High Impedance [READ] (Async Termination)
2
16
2
15
2
14
ns
39b
CS Negated to D15:0 High Impedance [READ] (Async Termination)
3
19
3
17
3
16
ns
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